Embodiments of the invention relate to capturing read data.
Referring to FIG. 1, a typical computer system may include at least one bridge 10 to establish communication between different buses of the computer system 10. For example, the bridge 10 may include a memory interface 14 and a local bus interface 18 for purposes of establishing communication between memory devices that are coupled to a memory bus 12 and a bus agent that is coupled to a local bus 20. In this manner, a processor 21 (a central processing unit (CPU), for example) may furnish signals to the local bus 20 for purposes of initiating a request (called a memory read request) to retrieve data from a system memory 11. The local bus interface 18 detects the request by decoding the signals from the local bus 20 and communicates an indication of the request to the memory interface 14. The memory interface 14, in turn, furnishes signals to the memory bus 12 to initiate a memory read operation with the memory 11. In this manner, in the course of the memory read operation, the memory 11 furnishes signals (to the memory bus 12) that indicate the requested data, and the memory interface 14 captures the data into a buffer 15 of the memory interface 14. The bridge 10 subsequently transfers the captured data (via a multiplexing circuit 16) from the buffer 15 to a buffer 19 in the local bus interface 18. Subsequently, the local bus interface 10 may generate signals on the local bus 20 that indicate the processor's requested data.
As an example, exemplary signals on the memory bus 12 for a memory burst read operation are depicted in FIGS. 2, 3, 4, and 5 for the scenario where the memory 11 is formed from double data rate (DDR) synchronous dynamic random access (SDRAM) memory devices. In particular, the memory interface 14 initiates the burst read operation by furnishing signals (to the memory bus 12) that indicate a read command, as depicted in FIG. 3. At time T0 on the positive edge of a memory bus clock signal (called CK (see FIG. 2)), a memory device (a memory module or memory chip, as examples) of the memory 11 latches the signals that indicate the read command, and the memory device begins responding to the burst read operation. In this manner, the memory device begins furnishing a data strobe signal called DQS (see FIG. 4) to a data strobe line of the memory bus 12 at time T1 by driving the DQS signal from a tri-stated level to a logic zero level.
From time T2 to time T6, the DQS signal (under the control of the memory device) follows the CK signal, and during this time interval, the memory device furnishes a different set of data (a sixty-four bit set of data, for example) to the data lines of the memory bus 12 on each positive and negative edge (i.e., on each strobe edge) of the DQS signal. For example, at time T2 beginning on the positive edge of the DQS signal, the memory device may furnish sixty-four bits of data (for a sixty-four bit data path, for example), and beginning at time T3, the memory devices may furnish another sixty-four bits of data. As an example, a data signal (called DQ) from a data bit line of the memory bus 12 is depicted in FIG. 5. The DQ signal indicates a bit of data during a data eye. Thus, for example, the data eye for a bit D0 occurs between times T2 and T3. Internally, the memory interface 14 may shift the DQS signal so that the strobe edges of the DQS signal are aligned in the center of the corresponding data eyes. Due to this arrangement, the edges may be used by the memory interface 14 to trigger the capture of data from the memory bus 12. At time T6, the memory device stops driving the data strobe line, and the DQS signal returns to the tri-stated level.
The bridge 10 may retrieve the data from the buffer 15 using either an internal clock domain that typically has a higher frequency (double the frequency, for example) than the clock domain of the memory bus 12 or by alternatively using a larger internal datapath. As a result, the memory interface 14 may wait for several internal clock cycles to ensure that the data in the buffer 15 is valid before retrieving the data from the buffer 15. Once the data is retrieved, the bridge 10 routes the data to the local bus interface 18 via a data path 17 (depicted in FIG. 1) that extends from the memory interface 14, through the multiplexing circuit 16 and then to the buffer 19 in the local bus interface 18. Unfortunately, the data path 17 may introduce a significant asynchronous propagation delay, and the buffer 19 may not latch valid data until several internal clock cycles (two, for example) have elapsed after the data leaves the buffer 15. The additional internal clock cycles that are needed to transfer the data between the buffers 15 and 19 may extend the time needed to satisfy the read request.
Thus, there is a continuing need for a bridge that responds in a more timely fashion to a memory read request.